1. Field of the Invention
This invention relates generally to computer processor pipeline control, and more particularly, to a system and method for controlling the pipeline of a multithreaded computer processor to ensure that deterministic execution of the threads is not affected by pipeline hazards.
2. Description of the Related Art
In a pipelined computer processor, pipeline hazards may reduce the performance of software codes. A typical cause of a pipeline hazard is that an instruction needs to use a result that is not yet available from a preceding instruction that is concurrently executed in the same pipeline. In a single-threaded pipeline, a conventional method of resolving the pipeline hazard is to stall the pipeline at the stage holding the instruction until the preceding instruction completes execution and the result is available.
However, this method, if used in a multi-threaded pipeline processor, can affect the real-time performance of other threads in the pipeline. In one application, a pipelined computer processor schedules the execution of two types of threads: hard-real-time (HRT) threads and non-real-time (NRT) threads. HRT threads require that a minimum number of instructions be executed per second to satisfy hard timing requirements, which may be imposed by standards such as IEEE 802.3 (Ethernet), USB, HomePNA 1.1 or SPI (Serial Peripheral Interface). NRT threads are programmed to perform those tasks having no hard timing requirements. Therefore, they can be scheduled in any clock cycle where there are no HRT threads actively running. Since the allocation of execution time for each HRT thread is set and the time required to execute each HRT thread is known, the deterministic performance of HRT threads is affected when the pipeline is stalled to remove the hazard.
Another method of resolving a pipeline hazard is to delay the instruction that encounters a hazard, and to allow other instructions to complete execution before the delayed instruction. However, this method requires complex and costly hardware to implement.
Accordingly, what is needed is a pipeline control mechanism to cope with pipeline hazard in a pipelined computer processor, for example, a multithreaded processor, to ensure deterministic execution of multiple threads. The pipeline control mechanism should also be easy and less expensive to implement than conventional systems.